#fpga

6 collections 6 auteurs 6 ouvrages trié(s) par

PROYECCIÓN, DISEÑO Y CONSTRUCCIÓN DE PLATAFORMA ROBÓTICA PARA INVESTIGACIÓN EN INTELIGENCIA ARTIFICIAL(Projection, design and construction of robotic platform for artificial intelligence research)

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PROYECCIÓN, DISEÑO Y CONSTRUCCIÓN DE PLATAFORMA ROBÓTICA PARA INVESTIGACIÓN EN INTELIGENCIA ARTIFICIAL(Projection, design and construction of robotic platform for artificial intelligence research)

Fredy

PROYECCIÓN, DISEÑO Y CONSTRUCCIÓN DE PLATAFORMA ROBÓTICA PARA INVESTIGACIÓN EN INTELIGENCIA ARTIFICIAL(Projection, design and construction of robotic platform for artificial intelligence research)

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Autres

PROYECCIÓN, DISEÑO Y CONSTRUCCIÓN DE PLATAFORMA ROBÓTICA PARA INVESTIGACIÓN EN INTELIGENCIA ARTIFICIAL(Projection, design and construction of robotic platform for artificial intelligence research)

Fredy

11 pages

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Ant colony technologies for image processing ; Skruzdžių kolonijų technologijos vaizdams apdoroti

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Ant colony technologies for image processing ; Skruzdžių kolonijų technologijos vaizdams apdoroti

Ant colony technologies for image processing ; Skruzdžių kolonijų technologijos vaizdams apdoroti

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Savoirs

Ant colony technologies for image processing ; Skruzdžių kolonijų technologijos vaizdams apdoroti

24 pages

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Novel data storage for H.264 motion compensation: system architecture and hardware implementation

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Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Matei Elena, Bauwelinck Johan, Cautereels Paul, De, Van

Novel data storage for H.264 motion compensation: system architecture and hardware implementation

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Savoirs

Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Matei Elena, Bauwelinck Johan, Cautereels Paul, De, Van

12 pages

English

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An FPGA-based processing pipeline for high-definition stereo video

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An FPGA-based processing pipeline for high-definition stereo video

Greisen Pierre, Heinzle Simon, Gross Markus, Burg

An FPGA-based processing pipeline for high-definition stereo video

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Savoirs

An FPGA-based processing pipeline for high-definition stereo video

Greisen Pierre, Heinzle Simon, Gross Markus, Burg

13 pages

English

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Parallel computations on pedigree data through mapping to configurable computing devices

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Parallel computations on pedigree data through mapping to configurable computing devices

Henshall, Little, Little Bryce

Parallel computations on pedigree data through mapping to configurable computing devices

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Savoirs

Parallel computations on pedigree data through mapping to configurable computing devices

Henshall, Little, Little Bryce

15 pages

English

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Design and implementation of a real time and train less eye state recognition system

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Design and implementation of a real time and train less eye state recognition system

Dehnavi Mohammad, Eshghi, Eshghi Mohammad

Design and implementation of a real time and train less eye state recognition system

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Savoirs

Design and implementation of a real time and train less eye state recognition system

Dehnavi Mohammad, Eshghi, Eshghi Mohammad

12 pages

English

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