Tutorial
CASPER Reference Design
Author: Henry Chen
December 18, 2009 (v1.1)
Hardware Platforms Used: IBOB
FPGA Clock Rate: 100MHz
Sampling Rate: N/A
Software Environment: TinySH
This tutorial walks through the process of building a Simulink design with Xilinx System
Generator, simulating it, and compiling to an FPGA bitstream using the bee_xps toolflow. The
design uses an addressable ROM to generate a pattern of bits which are output to LEDs on an
IBOB.
Creating the Design
Start Matlab, making sure that library paths are properly set (see Toolflow Setup Manual), and
run Simulink by typing simulink in the Matlab command prompt. To create a new design,
select File New Model from the Simulink Library Browser. Save as “casper_tutoria.mdl”
in a directory whose path has no spaces and is not a UNC path (\\somedrive\somefolder\...)
Open the Xilinx Blockset library, and from Basic Elements drag a new System Generator
block into the design.
CASPER Reference Design
Tutorial (v1.1) December 18, 2009 1
All designs using System Generator and blocks from the Xilinx Blockset need the System
Generator block. Settings in the block will be modified automatically by the toolflow, so you can
just insert the block and leave it alone.
CASPER Reference Design
Tutorial (v1.1) December 18, 2009 2
Next, insert an XSG core config block from the BEE_XPS System Blockset library. This block
is required by the bee_xps toolflow, and is used to define ...
Voir