Verilog TutorialAbdul-Rahman ElshafeiCOE-561IntroductionPurpose of HDL:1. Describe the circuit in algorithmic level (like c) and in gate-level (e.g. And gate)2. Simulation3. Synthesis4. Words are better than picturesNov 16, 2006 Abdul-Rahman Elshafei 21„„„„The best way to describe a circuit?If both inputs are 1, change both outputs.If one input is 1 change an output as follows:If the previous outputs are equalchange the output with input 0;If the previous outputs are unequalchange the output with input 1.If both inputs are 0, change nothing.3Nov 16, 2006 Abdul-Rahman ElshafeiLexicographyComments:Two Types:// Comment/* These comments extendover multiple lines. Goodfor commenting out code */Character Set:0123456789ABCD..YZabcd...yz_$Cannot start with a number or $Nov 16, 2006 Abdul-Rahman Elshafei 42„„„„„„„„Data Typesmodule sample (a,b,c,d);Data Values:0,1,x,zinput a,b;Wire output c,d;- Synthesizes into wires- Used in structural code wire [7:0] b;Regreg c,d;- May synthesize into latches, flip-flops or wires- Used in procedural codeinteger k;Integer32-bit integer used as indexesInput, Output, inoutDefines ports of a module (wire by default)5Nov 16, 2006 Abdul-Rahman ElshafeiData ValuesNumbers: Parameters:Numbers are defined by number of bits parameter n=4;Value of 23: wire [n-1:0] t, d;5’b101115’d23 `define Reset_state = 0, state_B =1, 5’h17 Run_state =2, finish_state = 3;if(state==`Run_state)Constants ...
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