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SUAVE Tutorial: Peter Ashenden March 1999SUAVE: VHDL Extensionsfor System-Level ModelingPeter J. AshendenDept Computer ScienceUniversity of Adelaide, Australiapetera@cs.adelaide.edu.auwww.cs.adelaide.edu.au/~peteraMarch 1999In a Nutshell ...• VHDL is a standard hardware descriptionlanguage, and is good for– register transfer level and behavioral modeling– structural modeling• SUAVE makes it better!– at what it’s already good for– and for modeling large complex systems• SAVANT and University of AdelaideVHDL Extensions– SAVANT: Standard Analyzer of VHDL Applicationsfor Next-generation Technology•Phil Wilsey, U. CincinnatiSUAVE Tutorial: Peter Ashenden - March 1999 21SUAVE Tutorial: Peter Ashenden March 1999Current Design FlowsASICVHDL VITALRequirements Detailed RTL gate? SynthSpecification Design model netlistFPGASimulation Simulation 4TestBenchSUAVE Tutorial: Peter Ashenden - March 1999 3Future Design FlowsRequirements TestTestSpecification BenchSystem Design/codeDesign Synths/wmodelCosimulationCosimulation//SystemSystem Partition Simulation 4Formal ProofmodelASICsh/wDesign/Perf. RTLmodelSynth modelAnalysisFPGASUAVE Tutorial: Peter Ashenden - March 1999 42SUAVE Tutorial: Peter Ashenden March 1999High-Level Modeling• System-level models– describe behavior of complex systems at a highlevel of abstraction• Test benches– manage complex data sets and test sequences• It’s really software engineering!SUAVE Tutorial: Peter ...
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SUAVE Tutorial: Peter Ashenden
SUAVE: VHDL Extensions for System-Level Modeling
Peter J. Ashenden Dept Computer Science University of Adelaide, Australia petera@cs.adelaide.edu.au www.cs.adelaide.edu.au/~petera March 1999
In a Nutshell ... VHDL is a standard hardware description language, and is good for – register transfer level and behavioral modeling – structural modeling SUAVE makes it better! – at what it’s already good for – and for modeling large complex systems SAVANT andUniversity ofAdelaide VHDLExtensions – SAVANT:StandardAnalyzer ofVHDLApplications forNext-generationTechnology Phil Wilsey, U. Cincinnati SUAVE Tutorial: Peter Ashenden - March 1999
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Current Design Flows
VHDL VITALASIC RSepqeuciifriecamtieonnts?DesitganiledeDdoleRLTmSynthnliettetgsa FPGA Simulation Simulation✔ Test Bench
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Future Design Flows RequirementsTest SpecificationBench System Design/ Designs/wSynthcode model SmysotdeemlnniiooatuliPmaSitrtlaalt iPFsiomrumon/oCorfo✔ ASICs Perf.h/wDesign/ model RTL Analysis Synthmodel FPGA
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High-Level Modeling System-level models – describe behavior of complex systems at a high level of abstraction Test benches – manage complex data sets and test sequences It’s really software engineering!
SUAVE Tutorial: Peter Ashenden - March 1999
High-Level Modeling Support Need abstract data types (ADTs) to manage complexity – VHDL has poor encapsulation Need inheritance to classify abstractions and for re-use – object-oriented methods – VHDL has no form of inheritance Need late binding to support evolution – VHDL only has ad-hoc polymorphism subprogram overloading
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High-Level Modeling Support Need type-based genericity for re-use – VHDL only has constant-based genericity Need dynamic process creation to model dynamic reactive systems – VHDL only has static process creation Need abstract communication – VHDL communication is via “hardware” signals
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SUAVE Extensions SUAVE adds – secure ADTs: private types and private parts in packages – OO features: tagged types, type extension, inheritance, class-wide polymorphic types – type generics – generic packages and subprograms – channels and message passing – process declarations and instantiation The ADT, OO and generic extensions are based on ADA-95 – integrated cleanly into VHDL SUAVE Tutorial: Peter Ashenden - March 1999
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Language Design Principles Simplicity of mechanism Orthogonality of mechanism – with clearly defined interactions Integration with existing – semantic mechanisms – syntax – language philosophies
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Agenda
ADTs – private types and private parts in packages OO features – inheritance, tagged types, type extension, class-wide polymorphic types Type generics Generic packages and subprograms Communication – channels and message passing Processes – declarations and instantiation SUAVE Tutorial: Peter Ashenden - March 1999
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Abstract Data Types (ADTs) Key mechanism for managing complexity Consists of – encapsulated data type – visible set of operations ADT user can only manipulate data with the public operations – secure, prevents inadvertent corruption of state VHDL mechanism – type and operations declared in a package – operations implemented in the package body –type details can’t be hidden! SUAVE Tutorial: Peter Ashenden - March 1999
Package Example package _quetestues is uset.krow .stseall; constantmax size : positive := 100; _ typequeue_arrayis array(0tomax_size 1)oftest; typequeueis record head, tail : naturalrange0tomax_size 1; size : naturalrange0tomax_size; the_buffer : queue_array; end recordqueue; functionis_empty ( Q : queue )returnboolean; function : queue )_ (returnboolean; is full Q procedureadd ( Q :inoutqueue; item :intest ); procedureremove ( Q :inout :queue; itemouttest ); end packageq_eueu;s test
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Package Example use.seu wk.orstteue_qall; variableinit_test_queue : test_queues.queue;
if notis_full ( init_test_queue )then add ( init test_queue, next_test ); _ end if;
_ t_q 42; init tes ueue.size :=
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Private Types/Private Parts SUAVE strengthens encapsulation for ADTs Private types in packages – ADT user knows type name, but not details – declared using reserved wordprivate Private part in package declarations – delimits publicly visible from hidden aspects – separated by reserved wordprivate – allows analyzer to know sufficient details of private types to allocate storage
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Secure ADT Example packagetest_q ueuesis use.stset.krow all; typequeueis private; functionis empty ( Q : queue )returnboolean; _ ... private constantmax_size : positive := 100; typequeue_arrayis array(0tomax_size 1)oftest; typequeueis record head, tail : naturalrange0tomax_size 1; size : naturalrange0tomax_size; th _ q _array; e buffer : ueue end recordqueue; end package ettsq_eueu;s
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Limited Private Types Normal private types have predefined assignment and (in)equality operations – element-wise copy/comparison – may not be appropriate, eg for pointer-based types Alimited private type – cannot be assigned by ADT user – does not have predefined (in)equality – ADT can define them if appropriate Private type containing a pointer must say so – use reserved wordaccessin declaration – prevents use as type of signals SUAVE Tutorial: Peter Ashenden - March 1999
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Limited Private Type Example package test_uquese is uses.sttek.w roall; typequeueis limited access private; constantempty_queue : queue; procedurecopy ( from_Q :inqueue; to_Q :inoutqueue ); impure function=( L, R :i nqueue )returnboolean; impure function/=( L, R :i nqueue )returnboolean; ... private ... end packagetest queues; _
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Limited Private Type Example packageetts ues _queis ... private typequeue_element; typequeue_ptris accessqueue_element; typequeue_elementis record _ ; the test : test next_element, prev_element : queue_ptr; end recordqueue_element; typequeueis record head, tail : queue_ptr; end recordqueue; constantempty_queue : queue := queue(’null,null); end package teseuest_qu; SUAVE Tutorial: Peter Ashenden - March 1999
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Limited Private Type Example usework.test queues.all; _ variabletest_queue_1, test_queue_2 : test_queues.queue;
_queue_1 /= empty_queuethen iftest copy ( from_Q => test_queue_ , _ test_queue_2 ); 1 to Q => end if;
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Lightweight Packages Currently packages are design units in VHDL SUAVE allows packages to be declared in any declarative part – eg, inside entities, architectures, process, subprograms, other packages Package declaration and body must appear in the same declarative region Allows local ADTs Like class definitions in C++
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Package Example architecturebehavioralofmicrocontrolleris packagewordsis typewordis range0to2**16 1; function+( L, R :i nword )returnword;
end packagewords; package bodywordsis function+( L, R :i nword )returnwordis begin return(L + R)mod2**16; end function+;
end package bodywords;
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Package Example
usewords.all; signals : word;
begin ... end architectureorvi;al aheb
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